1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices and driving methods thereof. More particularly, the present invention relates to an LCD device capable of displaying video signals to a substantially uniform brightness while reducing power consumption and to a driving method thereof.
2. Description of the Related Art
Generally, liquid crystal display (LCD) devices display pictures by controlling light transmittance characteristics of liquid crystal material in accordance with applied electric fields. Accordingly, LCD devices typically include an LCD panel having a plurality of liquid crystal cells arranged in a matrix pattern, and a drive circuit for driving the LCD panel.
The LCD panel generally includes a plurality of gate lines; a plurality of data lines crossing the plurality of gate lines, wherein the liquid crystal cells are arranged at crossings of the gate and data lines; pixel electrodes connected to respective ones of the data lines; and a common electrode, wherein pixel electrodes and the common electrode generate electric fields that control the light transmittance characteristics of the liquid crystal material. Each liquid crystal cell includes a switching device such as a thin film transistor (TFT) having source and drain terminals that connect respective ones of the pixel electrode to corresponding data lines. Further, each TFT includes a gate terminal that is connected to a corresponding gate line.
The drive circuit generally includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially applies scan signals to the plurality of gate lines to sequentially drive rows of liquid crystal cells. Whenever a scan signal is applied to a gate line, the data driver simultaneously applies video signals to each of the data lines. Accordingly, the video signals applied by the data driver selectively generate electric fields between each pixel electrode and the common electrode. By generating the electric fields, light transmittance characteristics of liquid crystal material within the liquid crystal cells are selectively controlled to display images.
The TFTs within the related art LCD panel are either amorphous silicon-type or polycrystalline silicon-type TFTs, based on whether the semiconductor layer of the TFT is formed of amorphous silicon or polycrystalline silicon.
The semiconductor layer from which the amorphous silicon-type TFTs is amorphous in structure and is therefore thermodynamically stable. However, amorphous silicon-type TFTs have a relatively low charge mobility compared to polycrystalline silicon-type TFTs. As a result, amorphous silicon-type TFTs are difficult to incorporate into LCD panels having a high pixel density. Further, when amorphous silicon-type TFTs are used within the LCD panel, the aforementioned drive circuits (e.g., the gate driver and the data driver) must be separately fabricated and mounted onto the liquid crystal display panel. When drive circuits must be separately fabricated and subsequently mounted, the cost of fabricating the LCD device increases undesirably.
When, however, TFTs of the LCD panel are provided as polycrystalline silicon-type TFTs, the drive circuits can be beneficially formed directly on (i.e., integrated onto) the LCD panel. Accordingly, the fabricating cost of LCD devices having polycrystalline silicon-type TFTs is less than the fabricating cost of LCD devices having amorphous silicon-type TFTS. Moreover, polycrystalline silicon-type TFTs have a relatively high charge mobility compared to amorphous silicon-type TFTs, and are therefore easily incorporated into LCD panels having high pixel density devices. Due to their relatively high charge mobility, polycrystalline silicon-type TFTs have a faster response time than amorphous silicon-type TFTs. Based on the above, use of polycrystalline silicon-type TFTs is preferable to use of amorphous silicon-type TFTs.
FIG. 1 schematically illustrates a related art liquid crystal display (LCD) device incorporating polycrystalline silicon-type thin film transistors (TFTs).
Referring to FIG. 1, the related art LCD device incorporating polycrystalline silicon-type TFTs generally includes a LCD panel 10 having a picture display area 12, a gate shift register 16, and a sampling switch array 14; a printed circuit board (PCB) 20; a control chip 22 and a switch controller 24 mounted on the PCB 20, wherein a control circuit and a data driver integrated circuit (IC) (not shown) are integrated within the control chip 22 and wherein the switch controller 24 controls the sampling switch array 14; and a flexible printed circuit (FPC) film 18 electrically connecting the LCD panel 10 with the PCB 20. Although the switch controller 24 as illustrated in FIG. 1 is mounted on the PCB 20, the switch controller 24 can also be mounted directly on the liquid crystal display panel 10.
The picture display area 12 displays pictures via a plurality of liquid crystal cells LC arranged in a matrix pattern. Each liquid crystal cell LC includes a switching device such as a polycrystalline silicon-type TFT, wherein each TFT is arranged at crossings of gate lines GL and data lines DL. The data lines DL receive video signals applied from the sampling switch array 14 while the gate lines GL receive gate pulses applied from the gate shift register 16.
The gate shift register 16 shifts control signals (start pulses) applied by the control chip 22 to sequentially apply gate pulses to the gate lines GL.
Integrated with the control chip 22, the control circuit applies control signals necessary for driving the switch controller 24 and the gate shift register 16. Further, the control circuit applies externally supplied digital data signals to the data driver IC. The data driver IC converts digital data signals applied from the control circuit into analog video signals and applies the analog video signals to a plurality of data supply lines PD. The data driver IC sequentially applies m number of video signals (where m is an integer equal to or greater than 1) to the data supply lines PD. The m number of video signals applied to the data supply lines PD are then applied to the sampling switch array 14 via the FPC film 18.
The sampling switch array 14 then divides the m number of video signals applied from the data supply lines PD and applies the divided video signals to the data lines DL. To this end, and while referring to FIG. 2, the related art sampling switch array 14 typically includes a plurality of switching blocks 29 and 30, wherein each of the switching blocks 29 and 30 include m number of switching devices S1 to Sm provided as PMOS transistors.
As shown in FIG. 2, each of the switching devices S1 to Sm within a switching block is commonly connected to a single data supply line PD and to a unique data line DL. Further, each of the switching devices S1 to Sm within a switching block is connected to one of m number of control lines C1 to Cm. Accordingly, the switching devices S1 to Sm transmit the m number of video signals from a data supply line PD to m number of data lines DL.
Referring to FIG. 3, the switch controller 24 sequentially applies turn-on pulses TP to the m number of control lines C1 to Cm, wherein a turn-on pulse TP includes a voltage drop from a high voltage Vh to a low voltage Vl. Referring to FIG. 4, the switch controller 24 shown in FIG. 1 typically includes m number of level shifters 32l to 32m, wherein each level shifter receives a high voltage Vhi (10V), and a low voltage Vli (−8V), from a power source (not shown). In receipt of the high and low voltages Vhi and Vli, each level shifter applies a turn-on pulse TP to a corresponding control line C1 to Cm in accordance with control signals supplied by the control chip 22.
Referring to FIGS. 2 and 3, a process of applying video signals to the data lines DL will now be explained in greater detail.
Initially, the switch controller 24 applies a first turn-on pulse TP1 to the first control line C1. Applied to the first control line C1, the first turn-on pulse TP1 is applied to the gate terminals of the first switching devices S1, thereby turning the first switching devices S1 on. When the first switching devices S1 are turned on, video signals applied to data supply lines PD are applied to the data lines DL1, DLm+1, etc. Next, a second turn-on pulse TP2 is applied to the second control line C2 which, in turn, is applied to the gate terminals of the second switching devices S2, thereby turning the second switching devices S2 on. When the second switching devices S2 are turned on, the video signals applied to the data supply lines PD are applied to the data lines DL2, DLm+2, etc. The aforementioned process of applying turn-on pulses TP and video signals is repeated for each of the switching devices S1 to Sm such that video signals are sequentially applied to the data lines DL and a predetermined image is displayed by the picture display area 12.
Generally, liquid crystal cells LC within the picture display area 12 are driven according to an inversion driving method such as a frame inversion method, field inversion method, line (or column) inversion method, or dot inversion method.
According to the frame inversion method shown in FIGS. 5A and 5B, the polarity of video signals applied to the liquid crystal cells LC is inverted whenever a frame of the picture display area 12 changes from an odd numbered frames (as shown in FIG. 5A) to an even numbered frame (as shown in FIG. 5B). Similarly, according to the field inversion method, the polarity of video signals applied to one field of liquid crystal cells LC is opposite the polarity of video signals applied to another field of liquid crystal cells LC in a frame of the picture display area 12. Moreover, the polarity of the video signals applied to the fields of liquid crystal cells LC is inverted whenever a frame of the picture display area 12 changes. Driving liquid crystal cells LC according to either the frame or field inversion methods advantageously consumes a minimal amount of power compared to other inversion methods such as line (or column) and dot inversion methods. However, either an entirety of, or predetermined fields within, the picture display area 12 undesirably flicker during each frame when the liquid crystal cells LC are driven according to the frame and field inversion methods, respectively.
According to the line inversion method shown in the FIGS. 6A and 6B, the polarity of video signals applied to adjacent horizontal rows of liquid crystal cells LC is inverted. Moreover, the polarity of the video signals applied to the horizontal rows of liquid crystal cells LC is inverted whenever a frame of the picture display area 12 changes from an odd numbered frames (as shown in FIG. 6A) to an even numbered frame (as shown in FIG. 6B). Driving liquid crystal cells LC according to the line inversion method induces a flickering phenomenon that generates a horizontal stripe pattern due to crosstalk between horizontal rows of liquid crystal cells LC.
According to the column inversion method shown in FIGS. 7A and 7B, the polarity of video signals applied to adjacent vertical columns of liquid crystal cells LC is inverted. Moreover, the polarity of the video signals applied to the vertical columns of liquid crystal cells LC is inverted whenever a frame of the picture display area 12 changes from an odd numbered frames (as shown in FIG. 7A) to an even numbered frame (as shown in FIG. 7B). Driving liquid crystal cells LC according to the column inversion method induces a flickering phenomenon that generates a vertical stripe pattern due to crosstalk between vertical columns of liquid crystal cells LC.
According to the dot inversion method shown in FIGS. 8A and 8B, the polarity of video signals applied to adjacent horizontal rows and vertical columns of liquid crystal cells LC is inverted. Moreover, the polarity of the video signals applied to the horizontal rows and vertical columns of liquid crystal cells LC is inverted whenever a frame of the picture display area 12 changes from an odd numbered frames (as shown in FIG. 8A) to an even numbered frame (as shown in FIG. 8B).
Driving liquid crystal cells LC according to the dot inversion method substantially prevents the flicker phenomenon from being generated because crosstalk between horizontal rows and vertical columns of liquid crystal cells can be substantially offset. However, when driving the LCD device shown in FIG. 1 according to the dot inversion method, a voltage difference is generated between the data lines DL to which the positive and negative polarities video signals. As a result, the picture display area 12 displays images to a non-uniform brightness due to internal resistances within the switching devices S1 to Sm when the polarity of the video signals is inverted.
More specifically, switching devices S1 to Sm, which are turned on to apply the video signals to the data lines DL, have a turn-on resistance, R, whereinR□(L/W)×[μ×Cox×(Vgs−Vth)]−1and wherein, L represents the channel length of the switching device, W represents the channel width of the switching device, μ represents the charge mobility, Cox represents a capacitance value between the active semiconductor layer and an electrode of the switching device, Vgs represents the voltage applied between the gate terminal and the source terminal of the switching device, and Vth represents the threshold voltage of the switching device.
With the exception of Vgs, values of the variables mentioned above are determined according to the manner in which the switching device was manufactured. Accordingly, the turn-on resistance R of the switching device is made variable when the voltage Vgs, applied between the gate and source terminals of the switching device, changes.
FIG. 9 illustrates voltage differences generated between turn-on signals and video signals applied to PMOS switching devices within the sampling switch array shown in FIG. 1.
Upon driving the liquid crystal display device according to the dot inversion method, the positive and negative voltages are repeatedly applied to the switching devices S1 to Sm based on the common voltage Vcom.
Referring to FIG. 9, when a first turn-on pulse TP1 having the low voltage V1 (−8V) is applied to the gate terminals of the PMOS switching devices S1 via a first control line C1, the PMOS switching devices S1 are turned on and a positive voltage is applied to corresponding data lines DL1, DLm+1, etc., connected to the turned-on PMOS switching devices S1. Accordingly, the Vgs value of the switching devices S1 has a voltage value of V1. When a second turn-on pulse TP2 having the low voltage V1 (−8V) is applied to the gate terminals of the PMOS switching devices S2 via a second control line C2, the PMOS switching devices S2 are turned on and a negative voltage is applied to corresponding data lines DL2, DLm+2, etc., connected to the turned-on PMOS switching devices S2. Accordingly, the Vgs value of the PMOS switching devices S2 has a voltage value of V2, wherein V2 is less than V1.
In view of the above, the turn-on resistance R of PMOS switching devices S change in accordance with the polarity of video signals to be applied to the corresponding data line DL. Accordingly, pictures are displayed within the picture display part 12 to a non-uniform brightness. Moreover, the turn-on resistance R of the PMOS switching devices S is inversely proportional to voltage of the video signal, wherein the PMOS switching device S has a high turn-on resistance R when a negative polarity video signal is applied to the data line DL and a low turn-on resistance when a positive polarity video signal is applied to the data line DL. Accordingly, as the turn-on resistance R increases, the power consumption of each PMOS switching device S increases and the time required to charge liquid crystal cells LC connected to each data line DL increases. As a result, undesirably large amounts of time and energy are required to charge externally applied video signals within the liquid crystal cells LC.
FIG. 10 illustrates voltage differences generated between turn-on signals and video signals applied to NMOS switching devices within the sampling switch array shown in FIG. 1.
As similarly described above, when a first turn-on pulse TP1 having a high voltage Vh (10V) is applied to the gate terminal of the NMOS switching device S1 via the first control line C1, the NMOS switching devices S1 are turned on and a positive voltage is applied to corresponding data lines DL1, DLm+1, etc., connected to the turned-on NMOS switching devices S1. Accordingly, the Vgs value of the switching devices S1 has the voltage value of V2. When a second turn-on pulse TP2 having the high voltage Vh (10V) is applied to the gate terminals of the switching devices S2 via the second control line C2, the NMOS switching devices S2 are turned on and a negative voltage is applied to corresponding data lines DL2, DLm+2, etc., connected to the turned-on NMOS switching devices S2. Accordingly, the Vgs value of the NMOS switching devices S2 has the voltage value of V1, wherein V1 is greater than V2.